This invention relates to a recording/reproducing system used in conjunction with a magnetic disk apparatus which reproduces data.
In the field of floppy disk apparatuses, a preceding-erase type magnetic head has recently been devised which is suitable for use with a high-density magnetic recording medium (disk). In the preceding-erase type magnetic head, an erase head is located in front of a read/write head in the rotational direction of the medium. Before new data are recorded in the medium by the read/write head, previously-recorded data are first erased by the erase head. When this type of magnetic head is employed, the erase head should preferably be turned on at a predetermined time before the recording of data on the medium, by the read/write head, begins, and turned off at a predetermined time before the recording of data ends. However, to be able to perform such a control procedure requires a controller, for turning the heads on and off, which is complicated in its construction. The conventional controller is incapable of performing such a control procedure, and for this reason, the erase head and the read/write head are turned on or off simultaneously.
Normally, a track has a format shown in FIG. 1A, i.e. in which one sector comprises an ID field and a data field.
The ID field comprises a synchronization area SYNC, an address mark area AM, an identification area ID, and a cyclic redundancy check area CRC. Information representative of the starting position and address of a sector are recorded in the ID field.
The data field stores data, and comprises synchronization area SYNC, address mark area AM, data area DATA, and cyclic redundancy check area CRC.
Synchronization areas SYNC of the ID field and the data field store synchronization data for a PLL circuit;
address mark areas AM store address mark data indicative of the starting position of the ID field or the data field;
ID area ID stores data such as the cylinder number, the side number, the sector number, and the length of the data field;
data area DATA stores data read out or written in by a user; and
cyclic redundancy check areas CRC store data for checking whether or not the data read out from the ID field or from data field contains an error.
Gaps 1, 2, 3, and 4 are areas for absorbing a fluctuation of rotation and an error in a mechanical alignment.
Read data reproduced from the recording medium by the magnetic head are supplied to a data separator which includes a PLL circuit and an external synchronization detecting circuit.
The external synchronization detector detects the synchronization data in the read data, and upon detection of the synchronization data, the PLL circuit begins oscillating in synchronism with the read data and outputs data pulses and clock pulses.
When the PLL circuit operates in synchronism with the read data, an internal synchronization detector detects the synchronization data, on the basis of the data pulse and the clock pulse, and a floppy disk controller checks whether or not the following data, other than synchronization data, are address mark data.
When the address mark data are detected, the floppy disk controller reads out the data stored in the ID area ID or in data area DATA, on the basis of the data pulses and clock pulses. When data other than the address mark data are detected, the floppy disk controller stops operating for a predetermined time period, and then repeats the above-mentioned operation.
FIGS. 1B and 1C show the positions where the erase head and read/write head of the preceding-erase type magnetic head are turned on and off, during the time which data writing operation by the floppy disk controller. As is shown in FIGS. 1A to 1C, DC erased areas are formed in Gap 3, where data are erased by the erase head and new data are not recorded.
In such a system, when data identical to the synchronization data are recorded in the data areas, a problem arises in that the external synchronization detection circuit sometimes erroneously detects the synchronization area of the recording medium, with the result that the system may fail to read out the data from the data area. Specifically, when zero pattern data having a predetermined byte length is stored in the data area DATA, the external synchronization detection circuit detects the zero pattern data as the synchronization data. In this case, the PLL circuit begins the synchronization operation. However, the internal synchronization detection circuit cannot detect the synchronization data, with the result that the PLL circuit continues to perform the synchronization operation. The PLL circuit oscillates at a frequency different from the frequency of normal read data, due to irregular pulses derived from the DC erased area. Consequently, there is the possibility that the PLL circuit will be unable to read out even the normal data.